#ifndef WIFI_H
#define WIFI_H

#include <stdint.h>

/* ══════════════════════════════════════════════
   Common defines
   ══════════════════════════════════════════════ */

/* PCI vendor IDs */
#define PCI_VENDOR_ID_INTEL     0x8086
#define PCI_VENDOR_ID_MEDIATEK  0x14c3

/* WiFi chip status */
enum wifi_state {
    WIFI_STATE_NONE = 0,
    WIFI_STATE_PCI_FOUND,
    WIFI_STATE_MMIO_READY,
    WIFI_STATE_FW_LOADED,
    WIFI_STATE_READY,
};

/* WiFi chip type */
enum wifi_chip_type {
    WIFI_CHIP_MT7922 = 0,
    WIFI_CHIP_INTEL_AX200,
    WIFI_CHIP_INTEL_AX201,
    WIFI_CHIP_INTEL_AX210,
    WIFI_CHIP_INTEL_CNVI,    /* AC 9560/9260 etc */
};

/* ══════════════════════════════════════════════
   MediaTek MT7922 defines
   ══════════════════════════════════════════════ */
#define MT7922_VENDOR_ID       0x14c3
#define MT7922_DEVICE_ID       0x7922

#define MT7922_FIRMWARE_WM     "WIFI_RAM_CODE_MT7922_1.bin"
#define MT7922_ROM_PATCH       "WIFI_MT7922_patch_mcu_1_1_hdr.bin"

/* MT7922 DMA ring sizes */
#define MT7922_TX_RING_SIZE    256
#define MT7922_TX_MCU_RING_SIZE 32
#define MT7922_TX_FWDL_RING_SIZE 8
#define MT7922_RX_RING_SIZE    512
#define MT7922_RX_MCU_RING_SIZE 32

#define MT_RX_BUF_SIZE         1856

/* MT7922 DMA ring bases */
#define MT_TX_RING_BASE        0x40000
#define MT_RX_DATA_RING_BASE   0x50000
#define MT_RX_EVENT_RING_BASE  0x54000

/* MT7922 MCU queue indices */
enum mt76_mcu_queue {
    MT_MCUQ_WM = 0,
    MT_MCUQ_FWDL,
    MT_MCUQ_TA,
};

enum mt76_rxq_id {
    MT_RXQ_MCU = 0,
    MT_RXQ_MCU_WA,
    MT_RXQ_MAIN,
};

/* MT7922 MCU TXD (connac2 long format) */
struct mt76_connac2_mcu_txd {
    uint32_t txd[8];
    uint16_t len;
    uint16_t pq_id;
    uint8_t  cid;
    uint8_t  pkt_type;
    uint8_t  set_query;
    uint8_t  seq;
    uint8_t  uc_d2b0_rev;
    uint8_t  ext_cid;
    uint8_t  s2d_index;
    uint8_t  ext_cid_ack;
    uint32_t rsv[5];
} __attribute__((packed));

/* MT7922 MCU RXD (connac2) */
struct mt76_connac2_mcu_rxd {
    uint32_t rxd[6];
    uint16_t len;
    uint16_t pkt_type_id;
    uint8_t  eid;
    uint8_t  seq;
    uint8_t  option;
    uint8_t  rsv;
    uint8_t  ext_eid;
    uint8_t  rsv1[2];
    uint8_t  s2d_index;
};

/* MT7922 MCU command IDs */
#define MCU_CMD_TARGET_ADDRESS_LEN_REQ  0x01
#define MCU_CMD_FW_START_REQ            0x02
#define MCU_CMD_NIC_POWER_CTRL          0x04
#define MCU_CMD_PATCH_START_REQ         0x05
#define MCU_CMD_PATCH_FINISH_REQ        0x07
#define MCU_CMD_PATCH_SEM_CONTROL       0x10
#define MCU_CMD_FW_SCATTER              0xee
#define MCU_CMD_RESTART_DL_REQ          0xef

#define MCU_EXT_CMD_EFUSE_ACCESS        0x01
#define MCU_EXT_CMD_CHANNEL_SWITCH      0x08
#define MCU_EXT_CMD_THERMAL_CTRL        0x2c

#define MCU_UNI_CMD_DEV_INFO_UPDATE     0x01
#define MCU_UNI_CMD_BSS_INFO_UPDATE     0x02
#define MCU_UNI_CMD_STA_REC_UPDATE      0x03

#define MCU_CE_CMD_GET_NIC_CAPAB        0x8a
#define MCU_CE_CMD_SET_RX_FILTER        0x0a
#define MCU_CE_CMD_SET_BSS_CONNECTED    0x16
#define MCU_CE_CMD_FWLOG_2_HOST         0xc5

#define MCU_PKT_ID                      0xa0
#define S2D_INDEX_H2N                   0

/* MT7922 CONN_INFRA power control */
#define PCIE_LPCR_HOST_SET_OWN          (1 << 0)
#define PCIE_LPCR_HOST_CLR_OWN          (1 << 1)
#define PCIE_LPCR_HOST_OWN_SYNC         (3 << 8)

/* MT7922 WFDMA0 Glo config bits */
#define WFDMA_GLO_CFG_TX_DMA_EN         (1 << 0)
#define WFDMA_GLO_CFG_RX_DMA_EN         (1 << 2)
#define WFDMA_GLO_CFG_TX_WB_DDONE       (1 << 6)
#define WFDMA_GLO_CFG_RX_WB_DDONE       (1 << 9)
#define WFDMA_GLO_CFG_CLK_GAT_DIS       (1 << 24)
#define WFDMA_GLO_CFG_FIFO_DIS_CHECK    (1 << 5)
#define WFDMA_GLO_CFG_OMIT_TX_INFO      (1 << 28)
#define WFDMA_GLO_CFG_OMIT_RX_INFO_PFET2 (1 << 27)

/* MT7922 WFDMA0 interrupt masks */
#define MT7922_INT_TX_DONE_BAND0        (1 << 0)
#define MT7922_INT_TX_DONE_MCU          (1 << 1)
#define MT7922_INT_RX_DONE_DATA         (1 << 2)
#define MT7922_INT_RX_DONE_WM           (1 << 3)
#define MT7922_INT_RX_DONE_WM2          (1 << 4)
#define MT7922_INT_MCU_CMD              (1 << 26)

/* MT7922 CONN_ON misc */
#define MT_TOP_MISC2_FW_PWR_ON          (1 << 0)
#define MT_TOP_MISC2_FW_N9_RDY          (1 << 4)
#define WFSYS_SW_RST_B                  (1 << 0)
#define WFSYS_SW_INIT_DONE              (1 << 0)

/* ══════════════════════════════════════════════
   Intel iwlwifi defines
   ══════════════════════════════════════════════ */

/* Intel PCI device IDs */
#define INTEL_PCI_DEVICE(DEVICE)  PCI_VENDOR_ID_INTEL, DEVICE

/* AX200 */
#define INTEL_AX200_DEVICE        0x2723

/* AX201 */
#define INTEL_AX201_DEVICE        0x02F0
#define INTEL_AX201_DEVICE_2      0x9DB1  /* Comet Lake PCH-LP AX201 */

/* AX210 */
#define INTEL_AX210_DEVICE        0x2725

/* CNVi (AC 9560/9260) */
#define INTEL_CNVI_DEVICE         0xA370
#define INTEL_CNVI_DEVICE_2       0x34DC
#define INTEL_CNVI_DEVICE_3       0x9DC8  /* Cannon Point-LP CNVi (9560) */

/* Intel CSR registers (from iwl-csr.h) */
#define IWL_CSR_BASE             0x000
#define IWL_CSR_HW_IF_CONFIG_REG 0x000
#define IWL_CSR_INT              0x008  /* Interrupt status/ack */
#define IWL_CSR_INT_MASK         0x00C  /* Interrupt enable */
#define IWL_CSR_FH_INT_STATUS    0x01C
#define IWL_CSR_GP_CNTRL         0x024  /* General purpose control */
#define IWL_CSR_HW_REV           0x028  /* Hardware revision */
#define IWL_CSR_HW_REV_WA        0x02C  /* Hardware revision workaround */
#define IWL_CSR_DBG_HPET_MEM_REG 0x02C
#define IWL_CSR_UCODE_DRV_GP1    0x054  /* Driver-firmware mailbox */
#define IWL_CSR_UCODE_DRV_GP1_SET 0x058
#define IWL_CSR_UCODE_DRV_GP1_CLR 0x05C
#define IWL_CSR_GIO_CHICKEN_BITS 0x020
#define IWL_CSR_RESET            0x020
#define IWL_CSR_RESET_REG_FLAG_SW_RESET  (1 << 0)

/* CSR GP CNTRL bits */
#define IWL_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY  (1 << 0)
#define IWL_CSR_GP_CNTRL_REG_FLAG_INIT_DONE        (1 << 2)
#define IWL_CSR_GP_CNTRL_REG_FLAG_MAC_INIT         (1 << 8)
#define IWL_CSR_GP_CNTRL_REG_FLAG_RF_POWER         (1 << 27)
#define IWL_CSR_GP_CNTRL_REG_FLAG_HAP_WAKE_L1A     (1 << 31)

/* CSR GIO chicken bits */
#define IWL_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (1 << 3)

/* CSR HW IF config */
#define IWL_CSR_HW_IF_CONFIG_REG_HAP_WAKE          (1 << 21)
#define IWL_CSR_HW_IF_CONFIG_REG_PERSISTENCE_MODE   (1 << 24)

/* Interrupt bits */
#define IWL_CSR_INT_BIT_ALIVE         (1 << 0)
#define IWL_CSR_INT_BIT_FH_TX         (1 << 1)
#define IWL_CSR_INT_BIT_MSIX_FH_TX    (1 << 1)
#define IWL_CSR_INT_BIT_RX_DMA        (1 << 31)
#define IWL_CSR_INT_BIT_FH_RX         (1 << 31)
#define IWL_CSR_INT_BIT_RF_KILL       (1 << 7)
#define IWL_CSR_INT_BIT_HW_ERROR      (1 << 29)
#define IWL_CSR_INT_BIT_WAKEUP        (1 << 6)

/* FH (Flow Handler) registers */
#define IWL_FH_MEM_LOWER_BOUND       0x1000
#define IWL_FH_MEM_UPPER_BOUND       0x2000
#define IWL_FH_MEM_RCSR_CHNL0        (IWL_FH_MEM_LOWER_BOUND + 0x000)
#define IWL_FH_MEM_RCSRFHCHCONFIG    0x1A0  /* FH config */
#define IWL_FH_MEM_RCSRGP_CHNL0RPTR  0x1D4  /* Rx channel 0 read ptr */
#define IWL_FH_MEM_RCSRGP_CHNL0WPTR  0x1D8  /* Rx channel 0 write ptr */
#define IWL_FH_MEM_CBBC_0_15_LOWER   (IWL_FH_MEM_LOWER_BOUND + 0x9D0)
#define IWL_FH_MEM_CBBC_0_15_UPPER   (IWL_FH_MEM_LOWER_BOUND + 0x9F0)
#define IWL_FH_MEM_KW_BASE           (IWL_FH_MEM_LOWER_BOUND + 0x97C)

/* FH RX config register */
#define IWL_FH_RCSR_CHNL0_CONFIG_REG    (IWL_FH_MEM_RCSR_CHNL0)
#define IWL_FH_RCSR_CHNL0_RDPTR_REG     (IWL_FH_MEM_RCSR_CHNL0 + 0x10)
#define IWL_FH_RCSR_CHNL0_WRPTR_REG     (IWL_FH_MEM_RCSR_CHNL0 + 0x14)
#define IWL_FH_RCSR_CHNL0_STTS_WPTR_REG (IWL_FH_MEM_RCSR_CHNL0 + 0x20)
#define IWL_FH_RCSR_CHNL0_RBDCB_BASE_REG (IWL_FH_MEM_RCSR_CHNL0 + 0x04)
#define IWL_FH_RCSR_CHNL0_RBDCB_WPTR_REG (IWL_FH_MEM_RCSR_CHNL0 + 0x08)

/* FH RX config bits */
#define IWL_FH_RCSR_RX_CONFIG_REG_VAL_EN       (1 << 31)
#define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RDRB_EN  (1 << 29)
#define IWL_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN (1 << 31)
#define IWL_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (1 << 31)
#define IWL_FH_RCSR_RX_CONFIG_RB_SIZE_2K       (0x00000000)
#define IWL_FH_RCSR_RX_CONFIG_RB_SIZE_4K       (0x00000100)

/* FH config register (gen1/2 combined) */
#define IWL_FH_MEM_RCSR_CHNL0_CONFIG_REG       (IWL_FH_MEM_RCSR_CHNL0)
#define IWL_FH_MEM_RCSR_CHNL0_RDPTR_REG        (IWL_FH_MEM_RCSR_CHNL0 + 0x10)

/* FH Rx status */
#define IWL_FH_RSCSR_CHNL0_STTS_WPTR_REG  (IWL_FH_MEM_RCSR_CHNL0 + 0x020)
#define IWL_FH_RSCSR_CHNL0_STTS_RDPTR_REG (IWL_FH_MEM_RCSR_CHNL0 + 0x010)
#define IWL_FH_RSCSR_CHNL0_STTS_WPTR_MASK 0xFFFF

/* FH TX config */
#define IWL_FH_TCSR_CHNL_TX_CONFIG_REG    (IWL_FH_MEM_LOWER_BOUND + 0x010)
#define IWL_FH_TCSR_CHNL_TX_DMA_EN        (1 << 31)
#define IWL_FH_TCSR_CHNL_TX_CREDIT_EN     (1 << 28)

#define IWL_FH_TCSR_CHNL_TX_FHINT_MASK    (1 << 31)

/* HBUS (Host Bus) registers */
#define IWL_HBUS_TARG_PRPH_WADDR     0x444
#define IWL_HBUS_TARG_PRPH_RADDR     0x448
#define IWL_HBUS_TARG_PRPH_WDAT      0x44C
#define IWL_HBUS_TARG_PRPH_RDAT      0x450

/* APMG (power management) */
#define IWL_APMG_CLK_CTRL_REG        0x3000
#define IWL_APMG_PS_CTRL_REG         0x300C
#define IWL_APMG_CLK_ENABLE_REG      0x3014

/* CPU init */
#define IWL_UREG_CPU_INIT_RUN        0xa05c44

/* NMI */
#define IWL_UREG_NIC_SET_NMI_DRIVER  0xa05c10

/* MSI-X */
#define IWL_CSR_MSIX_INT_MASK        0x018
#define IWL_CSR_MSIX_FH_INT_MASK     0x01C
#define IWL_CSR_MSIX_HW_INT_CAUSES_AD 0x2808

/* Context Info v2 registers */
#define IWL_CSR_CTXT_INFO_BOOT_CTRL  0x000
#define IWL_CSR_CTXT_INFO_ADDR       0x118
#define IWL_CSR_IML_DATA_ADDR        0x120
#define IWL_CSR_IML_SIZE_ADDR        0x128
#define IWL_CSR_AUTO_FUNC_BOOT_ENA   (1 << 1)

/* RX queue sizes */
#define IWL_RX_QUEUE_SIZE            256
#define IWL_CMD_QUEUE_SIZE           32

/* TFD queue sizes */
#define TFD_QUEUE_CB_SIZE            256

/* RB (Receive Buffer) sizes */
#define IWL_RX_RB_SIZE_2K            0
#define IWL_RX_RB_SIZE_4K            (1 << 8)
#define IWL_RX_RB_SIZE_16K           (10 << 20)

/* Alive notification status */
#define IWL_ALIVE_STATUS_OK          0xCAFE
#define IWL_ALIVE_STATUS_ERR         0xDEAD

/* TFD (Transmit Frame Descriptor) */
struct iwl_tfh_tfd {
    uint16_t num_tbs;
    uint8_t  __pad[2];
    struct {
        uint16_t tb_len;
        uint64_t addr;
    } __attribute__((packed)) tbs[25];
    uint32_t __pad2;
} __attribute__((packed));

/* Interrupt mask values */
#define IWL_MSK_INT_MASK_DEF  (IWL_CSR_INT_BIT_FH_RX | IWL_CSR_INT_BIT_HW_ERROR | \
                               IWL_CSR_INT_BIT_ALIVE)

/* FW TLV types */
#define IWL_UCODE_TLV_INST      0x01
#define IWL_UCODE_TLV_DATA      0x02
#define IWL_UCODE_TLV_INIT      0x03
#define IWL_UCODE_TLV_INIT_DATA 0x04
#define IWL_UCODE_TLV_PAGING    0x0F

#define IWL_TLV_UCODE_MAGIC     0x01312001

/* ══════════════════════════════════════════════
   Common structures
   ══════════════════════════════════════════════ */

/* DMA descriptor (WFDMA) */
struct wfdma_tx_desc {
    uint32_t sdl;
    uint32_t addr;
};

struct wfdma_rx_desc {
    uint32_t sdl;
    uint32_t addr;
};

/* DMA ring */
struct wifi_dma_ring {
    volatile struct wfdma_tx_desc *tx;
    volatile struct wfdma_rx_desc *rx;
    void     *buf;
    uint32_t  phys;
    uint16_t  ring_size;
    uint16_t  head, tail;
    uint8_t   qid;
};

/* Intel command header */
struct iwl_cmd_header {
    uint8_t cmd;
    uint8_t group_id;
    uint16_t seqnum;
} __attribute__((packed));

/* Intel TLV ucode header */
struct iwl_tlv_ucode_header {
    uint32_t magic;
    uint32_t ver;
    uint32_t build;
    char     human_readable[64];
    /* struct iwl_ucode_tlv data[] follows */
} __attribute__((packed));

struct iwl_ucode_tlv {
    uint32_t type;
    uint32_t length;
} __attribute__((packed));

/* ══════════════════════════════════════════════
   Intel Context Info v2 structures
   ══════════════════════════════════════════════ */

/* Peripheral scratch control config */
struct iwl_prph_scratch_version {
    uint16_t mac_id;
    uint16_t version;
    uint16_t size;
    uint16_t reserved;
} __attribute__((packed));

struct iwl_prph_scratch_control {
    uint32_t control_flags;
    uint32_t control_flags_ext;
} __attribute__((packed));

struct iwl_prph_scratch_dram {
    uint64_t common;  /* fw section addresses for INIT phase */
} __attribute__((packed));

struct iwl_prph_scratch_ctrl_cfg {
    struct iwl_prph_scratch_version version;
    struct iwl_prph_scratch_control control;
    uint64_t debug_cfg;      /* hwm base addr */
    uint32_t debug_size;
    uint32_t debug_token;
    uint64_t free_rbd_addr;  /* RX buffer address */
    uint64_t reduce_power;   /* UEFI base addr */
    uint32_t reduce_size;
    uint32_t step_mbx_0;
    uint32_t step_mbx_1;
} __attribute__((packed));

struct iwl_prph_scratch {
    struct iwl_prph_scratch_ctrl_cfg ctrl_cfg;
    uint32_t fseq_override;
    uint32_t step_analog_params;
    uint32_t reserved[8];
    struct iwl_prph_scratch_dram dram;
} __attribute__((packed));

struct iwl_prph_info {
    uint32_t boot_stage_mirror;
    uint32_t ipc_status_mirror;
    uint32_t sleep_notif;
    uint32_t reserved;
} __attribute__((packed));

struct iwl_context_info_dram {
    uint64_t fw_init_addr;
    uint64_t fw_init_size;
    uint64_t fw_inst_addr;
    uint64_t fw_inst_size;
    uint64_t fw_data_addr;
    uint64_t fw_data_size;
} __attribute__((packed));

struct iwl_context_info_v2 {
    uint16_t version;
    uint16_t size;
    uint32_t config;
    uint64_t prph_info_base_addr;
    uint64_t cr_head_idx_arr_base_addr;
    uint64_t tr_tail_idx_arr_base_addr;
    uint64_t cr_tail_idx_arr_base_addr;
    uint64_t tr_head_idx_arr_base_addr;
    uint16_t cr_idx_arr_size;
    uint16_t tr_idx_arr_size;
    uint64_t mtr_base_addr;
    uint64_t mcr_base_addr;
    uint16_t mtr_size;
    uint16_t mcr_size;
    uint16_t mtr_doorbell_vec;
    uint16_t mcr_doorbell_vec;
    uint16_t mtr_msi_vec;
    uint16_t mcr_msi_vec;
    uint8_t  mtr_opt_header_size;
    uint8_t  mtr_opt_footer_size;
    uint8_t  mcr_opt_header_size;
    uint8_t  mcr_opt_footer_size;
    uint16_t msg_rings_ctrl_flags;
    uint16_t prph_info_msi_vec;
    uint64_t prph_scratch_base_addr;
    uint32_t prph_scratch_size;
    uint32_t reserved;
} __attribute__((packed));

/* RB status (mapped in host memory) */
struct iwl_rb_status {
    uint16_t closed_rb_num;
    uint16_t closed_fr_num;
    uint16_t finished_rb_num;
    uint16_t finished_fr_num;
    uint32_t __spare;
} __attribute__((packed));

/* Alive notification */
struct iwl_lmac_alive {
    uint32_t ucode_major;
    uint32_t ucode_minor;
    uint8_t  ver_subtype;
    uint8_t  ver_type;
    uint8_t  mac;
    uint8_t  opt;
    uint32_t timestamp;
    uint32_t error_event_table_ptr;
    uint32_t log_event_table_ptr;
    uint32_t cpu_register_ptr;
    uint32_t dbgm_config_ptr;
    uint32_t alive_counter_ptr;
    uint32_t scd_base_ptr;
    uint32_t st_fwrd_addr;
    uint32_t st_fwrd_size;
} __attribute__((packed));

struct iwl_umac_alive {
    uint32_t umac_major;
    uint32_t umac_minor;
    uint32_t error_info_addr;
    uint32_t dbg_print_buff_addr;
} __attribute__((packed));

struct iwl_alive_ntf {
    uint16_t status;
    uint16_t flags;
    struct iwl_lmac_alive lmac_data[2];
    struct iwl_umac_alive umac_data;
    uint32_t sku_id[3];
    uint64_t imr_base_addr;
    uint32_t imr_size;
    uint32_t imr_enabled;
    uint64_t platform_id;
} __attribute__((packed));

/* Context info v2 config bits */
#define IWL_CTXT_INFO_AUTO_FUNC_ENABLE   (1 << 0)
#define IWL_CTXT_INFO_EARLY_DEBUG        (1 << 4)

/* Prph scratch flags */
#define IWL_PRPH_SCRATCH_RB_SIZE_4K      (1 << 16)
#define IWL_PRPH_SCRATCH_MTR_MODE        (1 << 17)
#define IWL_PRPH_SCRATCH_MTR_FORMAT_256B  (3 << 18)
#define IWL_PRPH_SCRATCH_TOP_RESET       (1 << 30)

/* Prph scratch ext flags */
#define IWL_PRPH_SCRATCH_EXT_URM_FW      (1 << 4)

/* ══════════════════════════════════════════════
   WiFi device (unified)
   ══════════════════════════════════════════════ */

struct wifi_dev {
    enum wifi_state state;
    enum wifi_chip_type chip;

    /* PCI */
    uint8_t  bus, dev;
    volatile uint8_t *mmio;  /* BAR0 base */

    /* Chip info */
    uint16_t device_id;
    uint32_t hw_rev;

    /* MCU sequence number */
    uint8_t  mcu_seq;

    /* ── MediaTek specific ── */
    struct wifi_dma_ring mt_tx_data;
    struct wifi_dma_ring mt_tx_mcu;
    struct wifi_dma_ring mt_tx_fwdl;
    struct wifi_dma_ring mt_rx_data;
    struct wifi_dma_ring mt_rx_mcu;

    /* ── Intel specific ── */
    struct iwl_context_info_v2 *ctxt_info_v2;
    struct iwl_prph_scratch   *prph_scratch;
    struct iwl_prph_info      *prph_info;
    struct iwl_rb_status      *rb_status;
    uint32_t ctxt_info_dma;
    uint32_t prph_scratch_dma;
    uint32_t prph_info_dma;
    uint32_t rb_status_dma;

    /* RX buffers */
    void     *rx_buf;
    uint32_t  rx_buf_dma;
    uint32_t  rx_buf_count;
    uint32_t  rx_read_ptr;

    /* TX command queue */
    void     *tx_cmd_buf;
    uint32_t  tx_cmd_dma;
    uint16_t  tx_write_ptr;
    uint16_t  tx_read_ptr;

    /* Keep-warm buffer */
    void     *kw_buf;
    uint32_t  kw_dma;

    /* Firmware image */
    void     *iml_buf;
    uint32_t  iml_dma;
    uint32_t  iml_len;

    /* IWL FW data */
    uint32_t  scd_base_addr;
    int       alive_received;
};

int  wifi_init(void);
int  wifi_scan(void);
int  wifi_load_fw(const char *fw_name);
int  wifi_load_intel_fw(const char *iml_name);
int  wifi_load_mt_fw(const char *fw_name, const char *patch_name);

#endif
